1. Field of the Invention
The invention generally relates to electronics. In particular, the invention relates to wired transmitters or line drivers.
2. Description of the Related Art
The bandwidth requirements of networking and high-performance processing applications have been projected to continue to increase into the tens of giga bits per second (Gb/s) rates. For example, with reference to serial attached SCSI (SAS) standard, the SAS-2.0 standard defines the maximum data rate as 6 Gb/s, with 12 Gb/s slated to follow in the upcoming SAS-3.0 standard.
One of the limiting factors for high-speed serial links is the band-limited response of the transmission medium (or channel) which causes increasing signal attenuation at high frequencies. In addition, residual low-frequency signal energy from adjacent symbols can cause inter-symbol-interference (ISI), which can corrupt the “data eye” and lead to a reduced signal-to-noise ratio (SNR). ISI-induced SNR degradation can be effectively improved by various channel equalization techniques. More specifically, equalizers commonly compensate for the band-limited response by either de-emphasizing low-frequency power at the transmitter or amplifying high-frequency power at the receiver, both of which are limited by transmitted signal power reduction and receiver noise amplification, respectively. It has been demonstrated that combining transmitter and receiver equalizations can compensate up to 20-30 decibels (dB) of attenuation at the Nyquist frequency. See, for example, M. Meghelli, et al., A 10 Gb/s 5-Tap-DFE/4-Tap-FFE transceiver in 90 nm CMOS, in IEEE ISSCC Dig. Tech. Papers, February 2007, pp. 80-81 and R. Payne, et al., A 6.25-Gb/s binary transceiver in 0.13-μm MOS for serial data transmission across high loss legacy backplane channels, IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2646-2657, December 2005.
In future serial-link systems with data rates higher than currently used, the amount of attenuation at the Nyquist frequency could be worse than 30 dB because of (a) legacy backplanes that were not intended for use with the higher signaling frequency and/or (b) less appreciable improvements in the construction of the channel and its materials. See, for example, J Kim et al., A large-swing transformer-boosted serial link transmitter with >VDD swing, IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1131-1142, May 2007. For some systems, one solution for maintaining sufficient SNR at the receiver is to increase the signal power by transmitting relatively large voltage swings.
In high-speed data transmission, current-mode-logic (CML) style transmitters are frequently employed because they support high data rates and have an inherently low susceptibility to power supply noise. These advantages, however, come along with some drawbacks, such as relatively high static power consumption, headroom problems due to the lower supply voltage in newer technologies, and the inability to support different DC termination voltages as the output of the CML circuit is generally referenced to one of the two power supply rails.
Voltage-mode transmitters overcome these disadvantages with a CMOS-oriented design style, supporting many different termination voltages. Other advantages of the voltage-mode type of transmitter include its potential for low-power operation (for a given output swing, a voltage-mode driver with a differential RX termination enables a potential 4 fold reduction in drive power compared to a CML driver), and good technology scaling due to the high relative content of digital circuitry versus analog circuitry. These factors make voltage-mode transmitters particularly suitable for multi-standard I/O applications.
As discussed above, some standards call for larger vertical eye openings (that is, higher launch amplitude). Equation 1 expresses a typical maximum output amplitude of a voltage-mode transmitter as a function of various parameters.
                              V          Odiff                =                  2          ·          AVD          ·                                    R              L                                                      R                L                            +                              R                Odiff                                                                        Equation        ⁢                                  ⁢        1            
In Equation 1, the voltage VOdiff corresponds to the peak-to-peak differential output voltage, the voltage AVD corresponds to the supply voltage of the output driver, the resistance RL corresponds to the load impedance, such as, but not limited to 100 ohms (Ω), and the resistance ROdiff corresponds to the output impedance of the voltage-mode transmitter.
According to Equation 1, an increase in the launch amplitude of a voltage-mode driver can be can be accomplished in two different ways for a constant load impedance: 1) the value of the resistance ROdiff can be reduced, to some extent, by trading off a degraded return loss, or 2) the supply voltage AVD can be raised from the typical 0.9-1.0 V limit used for thin-oxide FETs in 40 nm technology to a value of 1.5 V or even higher. The second option can be used when output swing should be increased more that what the ROdiff/return loss tradeoff can provide. This creates new design constraints, such as the desirability to interface a high-voltage output driver to a low-voltage pre-driver. Electrical overstress (EOS) should also be taken into consideration.
One problem that can occur with voltage-mode transmitters is electromagnetic interference (EMI). EMI can be a difficult issue to resolve. EMI compliance requirements are seldom overlooked by product engineering in the specification phase, and EMI compliance is often considered only as an afterthought. EMI requirements typically cannot be waived. EMI compliance difficulties can lead to very expensive last minute shielding solutions or to expensive redesigns.